Why do we need assertions ?Īn assertion is nothing but a more concise representation of a functional checker. If such a scenario is never expected from the design, the property of the design that only valid instructions can be read from memory is violated and the assertion fails.Īs evident from the two examples above, properties of a given design is checked for by writing SystemVerilog assertions. For example, assume a small processor decodes instructions read from memory, encounters an unknown instruction and results in a fatal error.
If a property of the design that is being checked for by an assertion is forbidden from happening, the assertion fails. But if the design gets an ack on the fifth cycle, the property that an ack should be returned within 4 clocks is violated and the assertion fails. For example, assume the design requests for grant and expects to receive an ack within the next four cycles. If a property of the design that is being checked for by an assertion does not behave in the expected way, the assertion fails. Hence assertions are used to validate the behavior of a system defined as properties, and can also be used in functional coverage.
The behavior of a system can be written as an assertion that should be true at all times.
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